The single queue switch

In this paper we introduce a new approach to ATM switching. We propose an ATM switch architecture which: uses only a single shift-register-type buffering element to store and queue the cells; and within the same physical queue switches the cells by organizing them in logical queues destined to different output lines. The buffer is also a sequencer which allows flexible ordering the cells in each logical queue to achieve any appropriate scheduling algorithm. This switch is proposed for use as the building block of large-scale multi-stage ATM switches and as the scheduler/controller for the RAM-based switches. The single queue switch implements output queueing and performs full buffer sharing. The hardware complexity is low. The number of input and output lines can vary independently without affecting the switch core. The size of the buffering space can be increased by simply cascading the buffering elements to each other