Design for manufacturability characterization and optimization of mixed-signal IP

Author

McNamara, Patrick ; Saxena, Sharad ; Guardiani, Carlo ; Taguchi, Hiroshi ; Yoshida, Emiko ; Takahashi, Naoki ; Miyamoto, Koji ; Sugawara, Kenichi ; Matsunaga, Takeshi

Author_Institution

PDF Solution Inc., San Jose, CA, USA

fYear

2001

fDate

2001

Firstpage

271

Lastpage

274

Abstract

This paper presents results of applying a statistically based parametric yield modeling approach to quantify current manufacturing yield and potential yield improvement of mixed-signal blocks. This design for manufacturability methodology is used to statistically characterize and quantify parametric yield optimization of a 2-channel 9-bit DAC manufactured in a 0.4C μm CMOS process. Parametric yield loss characterization and optimization are validated in silicon to be 15% and 4%, respectively

Keywords

CMOS integrated circuits; circuit optimisation; circuit simulation; design for manufacture; industrial property; integrated circuit modelling; integrated circuit yield; mixed analogue-digital integrated circuits; statistical analysis; 0.4 micron; CMOS process; DAC; circuit optimization; design for manufacturability characterization; manufacturing yield; mixed-signal IP; mixed-signal blocks; statistically based parametric yield modeling; Circuit faults; Design for manufacture; Design optimization; Integrated circuit technology; Manufacturing processes; Pulp manufacturing; SPICE; Silicon; Vehicles; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929771

Filename

929771