Title :
Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder
Author :
Seki, K. ; Mikami, K. ; Baba, M. ; Shinohara, N. ; Suzuki, S. ; Tezuka, H. ; Uchino, S. ; Okada, N. ; Kakinuma, Y. ; Katayama, A.
Author_Institution :
Device Div., NEC Corp., Kanagawa, Japan
Abstract :
This paper describes a 10.7 Gb/s throughput FEC (Forward Error Correction) codec LSI for optical transmission systems. In order to reduce the power consumption and logic size, the FEC codec uses a time-multiplexed Reed-Solomon (RS) decoder, which is shared among 4 RS codewords and processes 5 parallel digits. The time-multiplexed RS decoder requires only 58% of the gates and 75% of the power consumption of the conventional decoder. As a result, the codec achieves a low power consumption of only 3.31 W and a low gate count of only 1.1 Mgates using 0.18 μm CMOS technology
Keywords :
CMOS digital integrated circuits; Reed-Solomon codes; codecs; decoding; forward error correction; large scale integration; optical communication equipment; time division multiplexing; 0.18 micron; 10.7 Gbit/s; 3.31 W; CMOS technology; FEC codec LSI; logic size; optical transmission systems; parallel digits; power consumption; time-multiplexed RS decoder; time-multiplexed Reed-Solomon decoder; Codecs; Decoding; Energy consumption; Forward error correction; Large scale integration; Logic; National electric code; Optical distortion; Optical noise; Wavelength division multiplexing;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929778
