Title :
Spur suppression technique for multiplied delay locked loop
Author :
Liu, Cheng-Yu ; Chen, Wei-Zen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
fDate :
Nov. 30 2011-Dec. 2 2011
Abstract :
This paper presents spur suppression technique for multiplied delay locked loop (MDLL), and a spur model of MDLL using Markov chain analysis. By randomly reloading the reference edge to the delay line, the reference spur caused by systematic timing error are reduced by more than 20 dB compared to a conventional MDLL. On the other hand, the rms jitter is reduced by half compared to a PLL without reference reload. The effectiveness of spur and noise reduction are verified by the proposed model and experimental results.
Keywords :
Markov processes; phase locked loops; MDLL; Markov chain analysis; PLL; multiplied delay locked loop; noise reduction; spur suppression technique; systematic timing error; Clocks; Delay lines; Jitter; Phase locked loops; Phase noise; Timing; MDLL; PLL; Reference Spur;
Conference_Titel :
Radio-Frequency Integration Technology (RFIT), 2011 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4577-0517-5
DOI :
10.1109/RFIT.2011.6141783
