DocumentCode
3190763
Title
A 10-bit 400-MS/s 36-mW interleaved ADC
Author
Huang, Yen-Chuan ; Lin, Chin-Yu ; Lee, Tai-Cheng
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2011
fDate
Nov. 30 2011-Dec. 2 2011
Firstpage
181
Lastpage
484
Abstract
A high-speed interleaved pipelined ADC employs a global track-and-hold (T/H) circuit in front of the ADC to avoid sampling time mismatches between channels. Each sub-channel ADC employs both opamp-and time-sharing techniques to reduce power consumption and silicon area. The proposed ADC has been fabricated in a 90-nm digital CMOS technology and occupies 0.38 mm2. It operates at 400 MS/s and achieves an SNDR of 53.0 dB while the power consumption is 36 mW including an on-chip reference buffer.
Keywords
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; reference circuits; sample and hold circuits; digital CMOS technology; interleaved pipelined ADC; on-chip reference buffer; opamp-sharing; power 36 mW; sampling time mismatche; size 90 nm; time-sharing techniques; track-and-hold circuit; CMOS integrated circuits; CMOS technology; Calibration; Capacitance; Clocks; Gain; Power demand; interleaved ADC; opamp sharing technique; pipelined ADC; time sharing technique;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio-Frequency Integration Technology (RFIT), 2011 IEEE International Symposium on
Conference_Location
Beijing
Print_ISBN
978-1-4577-0517-5
Type
conf
DOI
10.1109/RFIT.2011.6141797
Filename
6141797
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