Title :
High speed redundant adder and divider in output prediction logic
Author :
Guo, Xinyu ; Sechen, Carl
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
A redundant bit adder (RBA) and a divider, both implemented in output prediction logic (OPL), are presented. By combining the carry-free nature of the redundant number system and the high-speed characteristics of OPL, the performance of the arithmetic blocks was tremendously improved. Fabricated in 0.18μm/1.8V CMOS, the adder achieves a measured delay of 211ps (2.4 fanout-of-four inverter delays), which is significantly faster than any previously published RBAs. The divider implemented in the same technology can achieve an operating frequency of 1.25GHz.
Keywords :
CMOS logic circuits; adders; dividing circuits; high-speed integrated circuits; logic circuits; logic design; redundant number systems; 0.18 micron; 1.25 GHz; 1.8 V; CMOS; OPL; RBA; arithmetic blocks; high speed redundant adder; high speed redundant divider; inverter delay; output prediction logic; redundant bit adder; redundant number system; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Computer architecture; Delay; Frequency conversion; Inverters; Throughput; Very large scale integration;
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
DOI :
10.1109/ISVLSI.2005.38
