DocumentCode
3190902
Title
Sensing design issues in deep submicron CMOS SRAMs
Author
Natarajan, Aiyappan ; Shankar, Vijay ; Maheshwari, Atul ; Burleson, Wayne
fYear
2005
fDate
11-12 May 2005
Firstpage
42
Lastpage
45
Abstract
In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.
Keywords
CMOS logic circuits; CMOS memory circuits; SRAM chips; amplifiers; integrated circuit design; leakage currents; logic design; 70 nm; CMOS technology; bit-line leakage compensation; deep submicron CMOS SRAM; memory design; nanometer CMOS; sense-amplifiers; CMOS technology; Central Processing Unit; Circuit testing; Delay; Differential amplifiers; Latches; Leakage current; Random access memory; Temperature sensors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.67
Filename
1430108
Link To Document