Title :
Sensing design issues in deep submicron CMOS SRAMs
Author :
Natarajan, Aiyappan ; Shankar, Vijay ; Maheshwari, Atul ; Burleson, Wayne
Abstract :
In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; amplifiers; integrated circuit design; leakage currents; logic design; 70 nm; CMOS technology; bit-line leakage compensation; deep submicron CMOS SRAM; memory design; nanometer CMOS; sense-amplifiers; CMOS technology; Central Processing Unit; Circuit testing; Delay; Differential amplifiers; Latches; Leakage current; Random access memory; Temperature sensors; Voltage;
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
DOI :
10.1109/ISVLSI.2005.67
