DocumentCode
3190905
Title
7V tristate-capable output buffer implemented in standard 2.5 V CMOS process
Author
Prodanov, Vladimir ; Boccuzzi, Vito
Author_Institution
Lucent Technol. Bell Labs., Murray Hill, NJ, USA
fYear
2001
fDate
2001
Firstpage
497
Lastpage
500
Abstract
This paper describes high-voltage CMOS buffer architecture that uses low-voltage transistors. The voltage capability of the presented architecture is nearly three times larger than the voltage capability of the used MOSFET´s. This buffer topology could be used to provide 3.3 V compatibility of 1.2 V and 1.5 V digital ICs implemented in standard CMOS technology. A 7 V circuit-prototype was fabricated in 0.25 μm 2.5 V CMOS technology. Performed measurements demonstrate stress-free operation in both active and high-impedance mode
Keywords
CMOS digital integrated circuits; buffer circuits; 0.25 micron; 1.2 to 7 V; 2.5 V; LV CMOS buffer architecture; active mode; digital ICs; high-impedance mode; high-voltage CMOS buffer; low-voltage transistors; tristate-capable output buffer; CMOS process; CMOS technology; Circuit topology; Driver circuits; MOSFETs; Performance evaluation; Production; Semiconductor device measurement; Stress measurement; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location
San Diego, CA
Print_ISBN
0-7803-6591-7
Type
conf
DOI
10.1109/CICC.2001.929829
Filename
929829
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