Title :
Power efficiency modeling and optimization of high-speed equalized-electrical I/O architectures
Author :
Palaniappan, Arun ; Palermo, Samuel
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas A & M Univ., College Station, TX, USA
Abstract :
An I/O design framework is presented which combines statistical link analysis with circuit power models to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate, channel, and process node.
Keywords :
circuit optimisation; high-speed integrated circuits; power integrated circuits; statistical analysis; I/O design framework; circuit power models; circuit style; high-speed equalized-electrical I/O architectures; optimization; power efficiency modeling; power-optimum equalization architecture; statistical link analysis; CMOS integrated circuits; Computer architecture; Decision feedback equalizers; Integrated circuit modeling; Optimization; Receivers; Transmitters; Electrical Interconnects; High-Speed I/O Link; Power Efficiency Modeling and Optimization;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-6865-2
Electronic_ISBN :
978-1-4244-6866-9
DOI :
10.1109/EPEPS.2010.5642533
