Title :
Shared data line technique for doubling the data transfer rate per pin of differential interfaces
Author :
Hatori, Fumitoshi ; Kousai, Shouhei ; Unekawa, Yasuo
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A technique for almost doubling the data transfer rate per pin of the differential interfaces has been proposed. In this technique the number of the differential transmission lines between transmitter LSI and the receiver LSI are shared with adjacent buffers to increase the transfer rate per pin. Each receiver consists of two comparators and a decoder circuit translates the signal voltage at the receiver end of the transmission line into digital data. A data rate of 1.1 Gbps/pin has been achieved in the fabricated test circuit in CMOS technology
Keywords :
CMOS digital integrated circuits; decoding; large scale integration; receivers; transmitters; 0.25 micron; 1.1 Gbit/s; comparators; data transfer rate doubling; data transfer rate per pin; decoder circuit; differential data I/O interfaces; differential transmission lines; receiver LSI; shared data line technique; transmitter LSI; CMOS technology; Circuit noise; Circuit testing; Data communication; Decoding; Distributed parameter circuits; Large scale integration; Transmitters; Voltage; Working environment noise;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929830
