Signal integrity analysis of bus turn-around on a DDR3 SDRAM memory channel

This paper describes a system-level signal integrity analysis of bus turn-around for a DDR3 SDRAM [1] implementation supporting 3 DIMMs per channel operating at speeds up to 1333MT/s with dynamic on-die termination (ODT). The method provides facilities for arbitrary DIMM population and ordering, noise modeling within a data group, network excitation including dynamically controlled ODT timing, and post-processing of simulation results. The digital and analog aspects are closely linked by employing actual DDR3 SDRAM protocol and timing as read/write stimulus to a multi-conductor network noise model representing a single data group. Complex stimulus patterns are generated to aid in optimization of controller design and controller/DRAM ODT timing.