Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime

The reliability of FPGA based hardware designs is becoming a challenge with future device technologies and, in particular, for avionic and space applications where FPGAs might get exposed to high radiation levels. Typically, redundancy-based techniques are used to achieve fault-tolerant operation. However, hardware redundancy comes with an overhead in performance factors such as area requirement, latency and power consumption. Based on the observation that reliability requirements vary over time, we propose the concept of Dynamic Reliability Management (DRM). With DRM, we can optimize the tradeoff between reliability and performance factors at runtime. In this paper, we present the DRM concept and a DRM tool flow comprising a design time and a runtime part. At design time, we leverage and extend the BYU-LANL tool to automatically generate several implementations of a single hardware design at different reliability levels and consequently with different performance factors. At runtime, we rely on the ReconOS architecture and multithreaded programming model to switch among different reliability configurations. Finally, a case study is provided with analysis of the trade-offs for varying reliability configurations.