Title :
A 96-dB CMOS programmable gain amplifier for Low-IF GPS receiver
Author :
Liang, Dongguo ; Ye, Qing
Author_Institution :
Asic & Syst. Dept., Chinese Acad. of Sci., Beijing
Abstract :
A programmable gain amplifier (PGA) was designed for a low-IF GPS receiver. Linearity method which was based on the differential degeneration and gm boost structure was used in the circuit. Transistors which were working in the sub-threshold region were applied in the built-in DC-offset correction circuit. This PGA provided a 96-dB digitally controlled gain range with a step of 6-dB, and the overall gain accuracy was 0.03 dB. The 3dB bandwidth of the PGA was 300 MHz. The noise figure at the maximum gain was 23.7dB. The IIP3 was -5dBm for the minimum gain. The PGA was implemented in a 0.18 um CMOS process and approximately occupied 0.097 mm2. This PGA consumed 3.5 mA at a 1.8 V supply.
Keywords :
CMOS integrated circuits; Global Positioning System; differential amplifiers; intermediate-frequency amplifiers; low-power electronics; programmable circuits; radio receivers; transistor circuits; CMOS process; bandwidth 300 MHz; built-in DC-offset correction circuit; current 3.5 mA; differential degeneration; gain 0.03 dB; gain 96 dB; gm boost structure; linearity method; low-IF GPS receiver; noise figure 23.7 dB; programmable gain amplifier; size 0.18 mum; transistor; voltage 1.8 V; Bandwidth; Circuits; Digital control; Dynamic range; Electronics packaging; Global Positioning System; Linearity; Microelectronics; Resistors; Voltage;
Conference_Titel :
Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on
Conference_Location :
Fujian
Print_ISBN :
978-1-4244-2063-6
Electronic_ISBN :
978-1-4244-2064-3
DOI :
10.1109/ICCCAS.2008.4657737
