DocumentCode :
3191202
Title :
Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximation
Author :
Rodriguez-Garcia, A. ; Pizano-Escalante, L. ; Parra-Michel, R. ; Longoria-Gandara, O. ; Cortez, J.
Author_Institution :
Dept. of Electr. Eng., CINVESTAV-IPN, Zapopan, Mexico
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
1
Lastpage :
6
Abstract :
Division is an operation extensively used in architectures for digital signal processing algorithms, which in portable devices require an implementation using fixed-point format. In this paper, a novel fixed-point divider is proposed. The divider architecture is based on a division algorithm that uses the reciprocal operation and a post-multiplication. In turn, reciprocal operation is based on the Newton-Raphson algorithm, where the seed is provided through piecewise polynomial approximation. Reciprocal operation is performed with only two clocks cycles and division operation requires only three clock cycles. A comparison between the proposed architecture and dividers based on coordinate rotation digital computer, shows that the proposed architecture achieves approximately 5-fold gain in execution time for applications in 50-100 MHz frequency range and higher signal-to-quantization-noise ratio.
Keywords :
digital signal processing chips; fixed point arithmetic; polynomial approximation; Newton-Raphson method; digital computer; digital signal processing algorithms; division algorithm; fast fixed point divider; fixed point format; piecewise polynomial approximation; reciprocal operation; signal-to-quantization-noise ratio; Accuracy; Approximation methods; Clocks; Computer architecture; Hardware; Polynomials; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4799-2078-5
Type :
conf
DOI :
10.1109/ReConFig.2013.6732291
Filename :
6732291
Link To Document :
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