Investigating substrate coupling noise impact on low-power memory controller PHY interface using on-chip measurement structure

This paper experimentally investigates substrate noise and its impact on the jitter performance of a low-power memory controller PHY interface using an on-chip substrate noise measurement structure. A previously proven on-chip supply noise measurement method is extended with minimum modification in the sensing front end to characterize the substrate noise. The implemented structure achieves the voltage resolution finer than 150μV/LSB and the measurement bandwidth up to 10GHz. The substrate noise impact on the jitter performance of the low-power PHY interface running at 3.2Gbps is characterized in terms of Substrate Noise Induced Jitter (SNIJ) sensitivity.