Design Alternatives for Baseband GPS Receivers

The present paper carries out area/power studies on certain architectures of Global Positioning System (GPS) Receiver baseband section. Depending upon the application of GPS receivers, the basic constraints could include either one or a combination of (a) design for smallest area or cost (b) design for performance (accuracy) and (c) design for ultra low power operation. The present paper carries out FPGA and ASIC design space exploration and presents results which could help as guidelines in selecting different architectures for implementation. Specifically, the above said architectures are designed and verified in simulation for Actel FPGAs as well as 0.35um and 0.13um ASIC libraries. It was found that based on the optimization carried out for a specific architecture, one can obtain significant reduction in area as well as power consumption.