Title :
Iterative latency insertion method for large networks with low latency
Author :
Sekine, Tadatoshi ; Asai, Hideki
Author_Institution :
Grad. Sch. of Sci. & Technol., Shizuoka Univ., Hamamatsu, Japan
Abstract :
This paper describes an iterative version of a latency insertion method (LIM) to overcome limitations on a time step size of the basic LIM. First, a semi-implicit LIM is reviewed to introduce a basic algorithm of the LIM. Then, it is shown that the semi-implicit LIM is equivalent to the scheme based on a matrix splitting and a trapezoidal formula. After that, we propose the iterative LIM by expanding the matrix splitting scheme. Because iterative solutions in the iterative LIM converge to the solutions obtained by the trapezoidal formula, which is unconditionally stable scheme, the proposed method can use a larger time step size than the basic LIM. Numerical results show that the iterative LIM is about 7.4 times faster than the basic LIM with appropriate accuracy for simulations of the circuits with low latency.
Keywords :
circuit simulation; iterative methods; matrix algebra; circuit simulation; iterative latency insertion method; large networks; low latency; matrix splitting; semiimplicit LIM; trapezoidal formula; Capacitance; Inductance; Integrated circuit modeling; Iterative methods; Mathematical model; Topology; Transient analysis;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4244-6865-2
Electronic_ISBN :
978-1-4244-6866-9
DOI :
10.1109/EPEPS.2010.5642571