NoC-based hardware function libraries for running multiple DSP algorithms

Currently, application-specific systems on chip (SoC) require complex digital designs, causing the validation process to increment, affecting the ever-narrower time-to-market. An approach to deal with this issue consists of using already-validated IP cores interconnected by a network on chip (NoC). However, the NoC is mostly used as part of an application-specific design, which implies wasting time in configuring the NoC for a particular application. With the aim of hiding these management problems from high-level (software) designers, in this paper, the use of a NoC as a hardware function library provider is studied. This requires the introduction of a new entity into the NoC, here called the Feeder-Collector, that acts as an intermediary between the system and the NoC. The advantages of this approach are shown by means of a case study, where an ad hoc implementation in contrasted with the proposed NoC approach, for three digital signal processing algorithms. Results show that, on average, resource of 43.68% can be achieved by using the proposed approach, while at the same time, Non-Recursive-Engineering costs are reduced.