Optimal mapping of multiple packet lookup schemes onto FPGA

Nowadays Ethernet/IP based packet forwarding consists of a complex set of lookup schemes. A router/switch may have to support multiple such lookup schemes, depending on the location and specific operation of the device. Manual conversion of lookup schemes into a target architecture is slow and does not ensure an optimal allocation of FPGA resources for best performance. We develop an Integer Linear Programming (ILP) model for the problem of mapping complex lookup schemes onto FPGA while minimizing packet latency. The developed model is extended to provide support for both throughput-optimized and power-aware mapping. In all the cases, our formulation leads to optimal solution. We provide abstractions for representing lookup schemes and their corresponding implementation choices, and also for the FPGA devices and their power consumption. These abstractions simplify the description of lookup schemes, while preserving the necessary details, and thus reduce the solution time. We demonstrate the practicality of the developed model by optimally mapping several complex real world lookup schemes onto a state-of-the-art FPGA device using a popular ILP solver package. In all the cases, the execution time on a desktop workstation is under a minute.