DocumentCode :
3191755
Title :
Energy efficient architectures for the log-MAP decoder through intelligent memory usage
Author :
Atluri, Indrajit ; Kumaraswamy, Ashwin K. ; Chouliaras, V.A.
Author_Institution :
Sch. of Eng. & Electron., Edinburgh Univ., UK
fYear :
2005
fDate :
11-12 May 2005
Firstpage :
263
Lastpage :
265
Abstract :
Turbo decoding generally employs maximum a posteriori (MAP) and the soft output Viterbi (SOVA) algorithm in its soft-input soft-output (SISO) component decoders. This paper reformulates the implementation of a low power Log-MAP decoder with reduced storage requirement and based on the optimized MAP algorithm that calculates the reverse state metrics in the forward recursive manner. As a result, the authors present new low power derivatives of this decoder through a variation in the percentage of memory savings. Three low power architectures of the Log-MAP decoder not employing the sliding window technique have been developed and post layout power savings of approximately 44%, 40% and 36% with respect to the conventional implementation have been observed.
Keywords :
Viterbi decoding; circuit layout; hardware description languages; logic circuits; low-power electronics; maximum likelihood decoding; memory architecture; network synthesis; turbo codes; SISO; SOVA; Turbo decoding; decoder architecture; intelligent memory usage; log-MAP decoder; low power architectures; maximum a-posteriori; optimized MAP algorithm; sliding window technique; soft output Viterbi algorithm; soft-input soft-output component decoder; CMOS technology; Decoding; Energy consumption; Energy efficiency; Power engineering and energy; Probability; Telecommunication services; Turbo codes; Very large scale integration; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
Type :
conf
DOI :
10.1109/ISVLSI.2005.29
Filename :
1430147
Link To Document :
بازگشت