Power integrity characterization and correlation of 3D package systems using on-chip measurements

System power integrity characterization for low-power high-speed memory interface in a 3D package system is a challenging task due to probing difficulties imposed by small form factor. In this paper, power integrity measurements including supply noise, PSIJ sensitivity and PDN impedance curve using on-chip noise generator and monitors are presented. On-chip measurement data are validated by off-chip sense line measurements. Good correlations between simulation and measurements close the loop between analysis and verification for the system power supply delivery design.