ReCompAc: Reconfigurable compute accelerator

This paper presents a promising technique for accelerating frequently executed (hot) code regions. Unlike most accelerators which utilize dedicated hardware structures, our architecture exploits the available execution resources of a chip multiprocessor (CMP), while dynamically specializing into a reconfigurable compute accelerator. Execution units available in one or more general purpose cores are placed close to each other on the chip. An additional reconfigurable switched network is used to couple these units and to specialize the functionality of the accelerator for the hot code regions. The available general purpose hardware in cores executes memory instructions, feeds and controls the accelerator. Moreover, the CMP supports core fusion, and while fusing cores resources it allows for more aggressive memory processing for memory intensive applications. The dynamic specialization of available execution resources increases the performance and efficiency of CMP, while requiring minimal hardware modifications. Our initial results indicate a speedup of 7× compared to a general purpose execution.