Title :
Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior
Author_Institution :
ARM Inc., Irvine
Abstract :
This paper extends the existing synchronous dataflow (SDF) model to provide dynamic behavior and top down design with compile time deadlock detection and bounded buffer memory. We propose a new dataflow model called constant rate dataflow with intermediate ports (CRDF-IP) in which a component (or actor) can send and receive data to/from another actor through intermediate port during its execution. Since an actor can call another actor multiple times per execution, dynamic behaviors are easily specified without introducing run-time scheduler. Moreover, top-down design can be achieved by extracting a sub-actor from the top actor. This paper has proved that deadlock detection and buffer size computation can be performed at compile in CRDF-IP model. The proposed model has been implemented in a system level design platform in which H.263 video encoding algorithm is specified.
Keywords :
data flow analysis; operating systems (computers); video coding; H.263 video encoding; bounded buffer memory; code synthesis; constant rate dataflow; intermediate ports; run-time scheduler; synchronous dataflow; system level design; time deadlock detection; Data mining; Dynamic scheduling; Encoding; Hardware; High level languages; Motion estimation; Processor scheduling; Runtime; System recovery; System-level design; dynamic behavior; intermediate ports; model of computation; synchronous dataflow; t op down design;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479724