Timing error handling on CGRAs

Error-detection sequential (EDS) circuits are used to detect timing errors in electronic systems. This paper presents an EDS circuit that avoids the generation of false error signals on a coarse grained reconfigurable architecture (CGRA). In a first step we analyzed the timing error handling mechanism of EDS circuits and formulated - based on that analysis - the conditions that must be satisfied for EDS circuits to accomplish the avoidance of false error signals. In a second step we constructed an EDS circuit by means of these theoretical results and integrated this EDS circuit in a CGRA. Finally, we tested the CGRA by SPICE simulations. These simulations confirm that our EDS circuit implementation avoids false error signal generation on a CGRA.