Boundary Contour System for Dynamic Compression and Image Edge Enhancement

The Boundary Contour System (BCS) provides a powerful technique to recognize patterns and restore image quality under excessive fixed pattern noise as in Synthetic Aperture Radar (SAR) images. This paper describes the VLSI design of the circuits needed for preprocessing stages of BCS (i.e.) preprocessing noisy image data that vary in intensity over as much as four orders of magnitude. The circuits are based on equations representing a stage one of a BCS. The preprocessing stages have been designed using cadence spectre IC5 tool. The stage one model circuits with ID array of 20 node cells is designed which here demonstrates the dynamic range compression and the responses to input stimuli from the linear array of circuits illustrate edge enhancement.