• DocumentCode
    3191976
  • Title

    Balancing system level pipelines with stage voltage scaling

  • Author

    Guo, Hui ; Parameswaran, Sri

  • Author_Institution
    Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
  • fYear
    2005
  • fDate
    11-12 May 2005
  • Firstpage
    287
  • Lastpage
    289
  • Abstract
    This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in throughput and response time, and 11% improvement in power consumption can be achieved with limited memory overhead.
  • Keywords
    application specific integrated circuits; asynchronous circuits; logic partitioning; low-power electronics; memory architecture; memory overhead; power consumption; response time; stage supply voltages; stage voltage scaling; system level pipelines balancing; throughput; Australia; Computational modeling; Computer science; Delay; Design methodology; Energy consumption; Hardware; Pipeline processing; Throughput; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
  • Print_ISBN
    0-7695-2365-X
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2005.20
  • Filename
    1430158
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3191976