Title :
Balancing system level pipelines with stage voltage scaling
Author :
Guo, Hui ; Parameswaran, Sri
Author_Institution :
Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
Abstract :
This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in throughput and response time, and 11% improvement in power consumption can be achieved with limited memory overhead.
Keywords :
application specific integrated circuits; asynchronous circuits; logic partitioning; low-power electronics; memory architecture; memory overhead; power consumption; response time; stage supply voltages; stage voltage scaling; system level pipelines balancing; throughput; Australia; Computational modeling; Computer science; Delay; Design methodology; Energy consumption; Hardware; Pipeline processing; Throughput; Voltage;
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
DOI :
10.1109/ISVLSI.2005.20
