Full-Chip Leakage Verification for Manufacturing Considering Process Variations

Author

Li, Tao ; Yu, Zhiping

Author_Institution

Tsinghua Univ., Beijing

fYear

2008

fDate

17-19 March 2008

Firstpage

220

Lastpage

223

Abstract

A novel compact model for subthreshold leakage (I_sub) including its extraction scheme has been developed in this paper. Both quantum and stress effects have been covered in this model, and it accurately fits experiment data for both nMOSFETs and pMOSFETs. A study of subthreshold leakage variations (SLVs) for the 65 nm technology has been reported for the first time. Gate length (L) roughness and variations in V_th are found to account for most of the SLVs. With the proposed model, a statistical methodology has been developed to address the growing issue of full-chip leakage verification for actual- fabrication circuits.

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit modelling; leakage currents; manufacturing processes; nanoelectronics; statistical analysis; stress effects; MOSFET; actual- fabrication circuits; compact model; extraction scheme; full-chip leakage verification; gate length roughness; process variations; quantum effects; statistical methodology; stress effects; subthreshold leakage variations; CMOS technology; Circuit simulation; Leakage current; MOSFETs; Manufacturing processes; Microelectronics; Optical distortion; Semiconductor device modeling; Subthreshold current; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

978-0-7695-3117-5

Type

conf

DOI

10.1109/ISQED.2008.4479729

Filename

4479729