Scan Flip-Flop Ordering with Delay and Power Minimization during Testing

Scan chain design is a major issue in circuit testing to minimize test overheads like area, delay and power. A number of works have been presented in the literature to optimize either delay or power by scan-chain reordering. Reordering for power minimization has been criticized mostly as it modifies the scan delay significantly, increasing test time. This paper presents a Genetic Algorithm based formulation to provide a trade-off between delay and power minimization in scan chain reordering to come up with the order of flip-flops on the chain based upon a weighted cost function of delay and power consumption metrics.