Optimal signaling techniques for Through Silicon Vias in 3-D integrated circuit packages

We investigate optimal techniques for signaling over Through Silicon Vias (TSV) in 3-D circuits to derive design guidelines for maximizing data rate, energy and signal integrity. Low-voltage differential (LVDS) and low-voltage single-ended (LVSE), voltage mode (VM) and current mode (CM) drivers and receivers are implemented in a 65 nm CMOS technology and SPICE simulations with accurate TSV electrical models including coupling effects extracted from a commercial field solver. Trade-offs between the signaling circuits are discussed and the results quantified in terms of data rate, delay variation, noise amplitude and energy consumption.