Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions

Assertions are being used more and more in design verification. The next application of assertions seems to be hardware testing. In this paper we propose an efficient approach for selecting and synthesizing OVL assertions in order to use them in online testing domain. First, based on the ATPG results and fault simulation, we find a set of assertions which have a high fault coverage according to their hardware area. Then, instead of synthesizing each assertion separately, we merge similar assertions together and make a unified hardware checker so that we can attain minimal resource usage for assertion circuits and reduce hardware overhead.