• DocumentCode
    3192136
  • Title

    CMOS realization of online testable reversible logic gates

  • Author

    Vasudevan, D.P. ; Lala, P.K. ; Parkerson, J.P.

  • Author_Institution
    Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
  • fYear
    2005
  • fDate
    11-12 May 2005
  • Firstpage
    309
  • Lastpage
    310
  • Abstract
    Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.
  • Keywords
    CMOS logic circuits; logic gates; CMOS logic gates; circuit complexity; online testable reversible logic gates; online-testability; reversible digital circuits; CMOS logic circuits; Circuit testing; Energy dissipation; Logic circuits; Logic design; Logic devices; Logic gates; Logic testing; Quantum computing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
  • Print_ISBN
    0-7695-2365-X
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2005.23
  • Filename
    1430168
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3192136