DocumentCode
3192274
Title
Static ultra-low-voltage high-speed CMOS logic and latches
Author
Berg, Y.
Author_Institution
Dept. of Inf., Univ. of Oslo, Oslo, Norway
fYear
2010
fDate
27-29 Sept. 2010
Firstpage
115
Lastpage
118
Abstract
In this paper we present timing details for static ultra-low-voltage (ULV) CMOS inverters and latches. The logic presented resemble domino CMOS logic and is more than 10 times as fast as complementary CMOS for very low supply voltages. Static ULV inverters and latches are presented and preliminary simulated data are provided for a 90 nm TSMC CMOS process.
Keywords
CMOS logic circuits; flip-flops; invertors; TSMC CMOS process; ULV CMOS inverters; latches; resemble domino CMOS logic; size 90 nm; static ultra-low-voltage high-speed CMOS logic; CMOS integrated circuits; Clocks; Delay; Inverters; Latches; Logic gates; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location
Madrid
Print_ISBN
978-1-4244-6469-2
Type
conf
DOI
10.1109/VLSISOC.2010.5642610
Filename
5642610
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