Power-aware FPGA routing fabrics and design tools

The performance of field-programmable gate arrays (FPGAs) has been significantly improved due to a new process technology. However, several problems have arisen in the new generation FPGAs. Specifically, the issue of power consumption is a serious issue, because FPGAs have many routing resources. We report on the improvement of both the FPGA routing structure and electronic design automation (EDA) tools in order to solve this issue. In order to reduce the power consumption, high activity nets are assigned to low load lines, which is the routing structure used for small-world networks in FPGAs. In addition, the clustering and routing algorithms of the EDA tools are improved to complement the routing structure. This report demonstrates that the power can be reduced. Based on evaluation results, a maximum power consumption improvement of 48.4% was obtained, and the average improvement was 22.9% when using the proposed routing structure and EDA tools.