Fundamental limitations in the design of front end and back end plasma etch processes

In less than ten years, we will be approaching the limits of CMOS technology with typical gate transistor lengths of less than 30 nm. The definition of the transistor gate region remains one of the most critical steps of the front end part of the device fabrication process. In principle, anisotropic etching of the gate material is required to maintain the critical dimension of the gate as defined by the lithography. At present, the acceleration of the roadmap imposes definition of gate transistors with dimensions even smaller than the lithography resolution. One possible way to obtain smaller gate length is based on a new approach where the bottom of the gate is smaller in dimension than the top (“notched gate”). In the first part of this paper, we discuss the mechanisms involved in the “notched” gate approach. In the second part of the paper, we discuss the introduction of low-k dielectric materials in the back end part of a CMOS process. In particular, the etching mechanisms of a polymer-based material (SiLK^TM), considered one of the most promising intermetal dielectric materials, are discussed in detail