Correlation between soft breakdown and plasma process induced damage

Plasma induced damage (PID) may result in trapped oxide charge or interface states build-up, leading to the degradation of device electrical characteristics, such as transconductance decrease or threshold voltage shifts. Moreover, it can degrade device lifetime, resulting in early dielectric breakdown of the oxide, i.e., a reduction in time-to-breakdown or in charge-to-breakdown. In this paper, this failure mode is referred to as hard breakdown (HB). Usually, this kind of failure is studied by testing a large amount of devices, and treating data from a statistical point of view. Devices with ultra-thin gate oxide also show a quite worrisome failure mode known as soft breakdown (SB), which is commonly described as a sudden decrease (increase) in gate voltage (current) during a constant current (voltage) stress; after this event, gate voltage (current) shows a typical noisy behavior. If and how SB is related to plasma process induced damage is still an open question. In this work, we propose a stress-and-test methodology to investigate such a link