A new current-balance model for predicting charging damage during high-temperature plasma processes

We formulated a simple circuit model to investigate the mechanism of the charging damage during high-temperature plasma processes. This model only takes into account the balance of the current that comes into and goes out of the silicon substrate during PECVD. The current paths are plasma to substrate (and vice versa) and electrodes of the electrostatic chuck or susceptor to substrate (and vice versa). We determined the substrate potential with this circuit model and evaluated the degree of charging damage over a wafer. This simple circuit model shows that the low resistance between the substrate and the electrodes of the chuck or the susceptor drastically increases the charging damage of the gate oxides, but neither the clamp voltage of the dipole-type electrostatic chuck nor the leakage current influences the charging damage. These results agree fairly well with experimental measurements. The model also explains the experimental observation that a 100 nm thick oxide on the backside of the wafer significantly reduces the damage, but a thicker oxide only slightly reduces it