• DocumentCode
    319307
  • Title

    Streamlining inter-operation memory communication via data dependence prediction

  • Author

    Moshovos, Andreas ; Sohi, Gurindar S.

  • Author_Institution
    Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
  • fYear
    1997
  • fDate
    1-3 Dec 1997
  • Firstpage
    235
  • Lastpage
    245
  • Abstract
    We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operation memory communication. We use data dependence prediction to identify and link dependent loads and stores so that they can communicate speculatively without incurring the overhead of address calculation, disambiguation and data cache access. We also use data dependence prediction to convert, DEF-store-load-USE chains within the instruction window into DEF-USE chains prior to address calculation and disambiguation. We use true and output data dependence status prediction to introduce and manage a small storage structure called the transient value cache (TVC). The TVC captures memory values that are short-lived. It also captures recently stored values that are likely to be accessed soon. Accesses that are serviced by the TVC do not have to be serviced by other parts of the memory hierarchy, e.g., the data cache. The first two techniques are aimed at reducing the effective communication latency whereas the last technique is aimed at reducing data cache bandwidth requirements. Experimental analysis of the proposed techniques shows that: the proposed speculative communication methods correctly handle a large fraction of memory dependences; and a large number of the loads and stores do not have to ever reach the data cache when the TVC is in place
  • Keywords
    cache storage; instruction sets; memory architecture; performance evaluation; storage management; DEF-store-load-USE chains; address calculation; address disambiguation; communication latency; data cache access; data cache bandwidth requirements; data dependence prediction; instruction window; inter-operation memory communication; memory dependences; memory hierarchy design; storage management; transient value cache; Bandwidth; Cache storage; Communication effectiveness; Delay; Memory management; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on
  • Conference_Location
    Research Triangle Park, NC
  • ISSN
    1072-4451
  • Print_ISBN
    0-8186-7977-8
  • Type

    conf

  • DOI
    10.1109/MICRO.1997.645814
  • Filename
    645814