A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs

This paper presents a heuristic cell-based approach to reduce leakage power in multi-million gate design ASICs in 90 nm/65 nm processes by swapping low-Vt cells with high-Vt cells on less critical timing paths in the design. It uses heuristics to avoid frequent time-consuming full-design timing updates and has significant run-time improvement over currently available approaches. Unlike traditional approaches, proposed generic approach fits well in the design flow and works on any kind of design having mixture of all type of Vt cells available in the library. The proposed algorithm gives active leakage reduction of up to 64% with run time of 3-15 hours for multi-million gate designs.