Novel input coding technique for high-precision LUT-based multiplication for DSP applications

In this paper, we present a novel input-coding scheme for high-precision lookup-table (LUT)-based implementation of constant multiplications by input operand decomposition. Besides, we have described an efficient LUT design for the multiplication of input sub-words where the input coding technique is combined with the odd-multiple-storage technique to achieve the reduction of LUT size by a factor of ~ 4 over the conventional technique. Compared with the antisymmetric product coding (APC) scheme, the input coding scheme involves significantly less area and less time overheads. The proposed LUT-multiplier and the existing one are coded in VHDL and synthesized by Synopsys Design Compiler using 90 nanometer CMOS library. The proposed one is found to offer more than 28% saving of area-delay product over the existing LUT multiplier, in average, for word-sizes 8, 16 and 32.