• DocumentCode
    3193367
  • Title

    Novel ultra low-voltage and high speed domino CMOS logic

  • Author

    Berg, Y.

  • Author_Institution
    Dept. of Inf., Univ. of Oslo, Oslo, Norway
  • fYear
    2010
  • fDate
    27-29 Sept. 2010
  • Firstpage
    225
  • Lastpage
    228
  • Abstract
    In this paper we propose a novel ultra low-voltage and high speed domino CMOS logic style. The proposed logic style utilizes floating-gate transistors which are used to increase the current level of the transistors driving the output of the gates. In this way the delay of the proposed logic style may be reduced to less than 10% compared to standard CMOS.
  • Keywords
    CMOS logic circuits; floating-gate transistors; high speed domino CMOS logic; ultra low-voltage domino CMOS logic; CMOS integrated circuits; Clocks; Delay; Inverters; Logic gates; Noise; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
  • Conference_Location
    Madrid
  • Print_ISBN
    978-1-4244-6469-2
  • Type

    conf

  • DOI
    10.1109/VLSISOC.2010.5642664
  • Filename
    5642664
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3193367