On test compaction objectives for combinational and sequential circuits

Author

Pomeranz, Irith ; Reddy, Sudhakar M.

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1998

fDate

4-7 Jan 1998

Firstpage

279

Lastpage

284

Abstract

We study storage schemes for test patterns and test responses of combinational and synchronous sequential circuits which are tested off-line by a tester. These storage schemes provide new objectives for test compaction beyond the need to reduce the test set size as much as possible. We report on several postprocessing methods to reduce the storage requirements of a given test set and present experimental evidence pointing to the possibility of reducing the storage requirements by using appropriate compaction objectives during test generation

Keywords

automatic testing; combinational circuits; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; combinational circuits; offline testing; postprocessing methods; storage requirement reduction; storage schemes; synchronous sequential circuits; test compaction; test generation; test pattern storage; test response storage; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Compaction; Costs; Petroleum; Sequential analysis; Sequential circuits; Synchronous generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Conference_Location

Chennai

ISSN

1063-9667

Print_ISBN

0-8186-8224-8

Type

conf

DOI

10.1109/ICVD.1998.646618

Filename

646618