A method for synchronizing IEEE 1149.1 test access port for chip level testability access

Author

Bhavsar, Dilip

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1998

fDate

4-7 Jan 1998

Firstpage

289

Lastpage

292

Abstract

This paper presents a novel method for using the industry standard IEEE Std. 1149.1 test port for accessing chip-wide testability features. The scheme reconfigures the test port to switch its normal asynchronous-to-chip-logic operating mode to a special synchronous-to-chip-logic operating mode that can be exploited in chip-alone test environments. The method allows the internal testability features to be designed normally and operated at full speed in chip´s native clock domain

Keywords

IEEE standards; built-in self test; design for testability; digital integrated circuits; integrated circuit testing; logic testing; synchronisation; BIST; DFT; IEEE 1149.1 test access port; JTAG; asynchronous-to-chip-logic operating mode; chip level testability access; chip-alone test environments; internal testability features; synchronous-to-chip-logic operating mode; test port reconfiguration; Assembly; Clocks; Logic design; Logic testing; Manufacturing; Registers; Semiconductor device testing; Switches; Synchronization; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Conference_Location

Chennai

ISSN

1063-9667

Print_ISBN

0-8186-8224-8

Type

conf

DOI

10.1109/ICVD.1998.646620

Filename

646620