• DocumentCode
    3193428
  • Title

    Techniques for Early Package Closure in System-in-Packages

  • Author

    Vaidyanathan, Santhosh C. ; Brahme, Amit M. ; Jairam, S.

  • fYear
    2008
  • fDate
    17-19 March 2008
  • Firstpage
    608
  • Lastpage
    613
  • Abstract
    The two main forces pushing package technologies to a new frontier are size and cost. The need of the hour is miniaturization, fuelled by rapidly growing complexity in the wireless phone market. CSP(chip scale packaging) has already reached 100% and further miniaturization can be achieved only by 3D packaging techniques. Complex 3D packaging techniques having hit the roadmap, the SoC design is largely driven by the co-dice that are stacked and the package elements such as size, routing layers, ball count etc. wherein "package-die co-design" is extremely critical for on time product delivery. In fact, it is not surprising that a SoC\´s floorplan is driven by package and "co-design" is an understatement. This paper highlights the importance of package-die co- design for early package closure in SIPs. Guidelines and solutions on the Periphery and package planning are included. Careabouts and tradeoffs when designing SIPs are also explained.
  • Keywords
    chip scale packaging; integrated circuit design; system-in-package; system-on-chip; 3D packaging techniques; CSP; SIP; SoC design; chip scale packaging; system-in-packages; wireless phone market; Assembly; Bonding; Chip scale packaging; Consumer electronics; Cost function; Electronics packaging; Guidelines; Instruments; Routing; Stacking; CSP; MCM; POP; SIP; SoC; landing; spacer;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-0-7695-3117-5
  • Type

    conf

  • DOI
    10.1109/ISQED.2008.4479807
  • Filename
    4479807