Title :
Design of low-complexity and high-speed digital Finite Impulse Response filters
Author :
Jaccottet, Diego ; Costa, Eduardo ; Aksoy, Levent ; Flores, Paulo ; Monteiro, Jose
Author_Institution :
Univ. Catolica de Pelotas, Pelotas, Brazil
Abstract :
In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a large number of constant multiplications, in the proposed method the constant multiplications are replaced by addition/subtraction and shift operations. Also, based on the design objective, i.e., low-complexity or high-speed, the addition/subtraction operations are implemented using Ripple Carry Adder (RCA) or Carry-Save Adder (CSA) architectures respectively. Furthermore, high-level algorithms designed for the optimization of the number of RCA and CSA blocks are used to reduce the complexity of the FIR filter. Thus, a Computer-Aided Design (CAD) tool that synthesizes low-complexity and high-speed FIR filters in a shift-adds architecture is developed. It is observed from the experimental results on FIR filter instances that the developed CAD tool can find better FIR filter designs in terms of area and delay than those obtained using efficient general multipliers.
Keywords :
FIR filters; adders; circuit CAD; circuit complexity; CAD tool; CSA architectures; FIR filters; RCA; carry-save adder architectures; computer-aided design tool; constant multiplication method; general multipliers; high-level algorithms; high-speed digital finite impulse response filters; low-complexity finite impulse response filter design; ripple carry adder; shift-add architecture; Adders; Algorithm design and analysis; Approximation algorithms; Delay; Finite impulse response filter; Logic gates; Optimization;
Conference_Titel :
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP
Conference_Location :
Madrid
Print_ISBN :
978-1-4244-6469-2
DOI :
10.1109/VLSISOC.2010.5642676