Technology scaling impact of variation on clock skew and interconnect delay

Author

Mehrotra, Vikas ; Boning, Duane

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

2001

fDate

6-6 June 2001

Firstpage

122

Lastpage

124

Abstract

Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both random and systematic variation in interconnect and device parameters as technology scales from 180 nm to 50 nm. For the case considered, we show that (1) clock skew increases from about 15% to 30% of the clock cycle, and (2) modeling systematic variation sources enables tighter tolerance design that can substantially reduce this skew as well as reduce wire length limitations.

Keywords

chemical mechanical polishing; circuit simulation; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; microprocessor chips; 180 to 50 nm; CD variation; H-tree; circuit simulation; clock skew; integrated variation analysis technique; interconnect delay; interconnect parameters; metal CMP; optimally buffered interconnect; random variation; systematic variation; technology scaling impact; tighter tolerance design; wire length limitations; Application software; Circuit optimization; Clocks; Copper; Delay lines; Frequency; Integrated circuit interconnections; Planarization; Repeaters; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International

Conference_Location

Burlingame, CA, USA

Print_ISBN

0-7803-6678-6

Type

conf

DOI

10.1109/IITC.2001.930035

Filename

930035