An optimal partition between on-chip and on-board interconnects

Author

Naeemi, Azad ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2001

fDate

6-6 June 2001

Firstpage

131

Lastpage

133

Abstract

An optimal partition between on-chip and on-board interconnects is proposed, which achieves the highest possible global clock frequency as well as high wiring density. A general model is developed for adequate number and size of repeaters and the impact of this model on optimal partition of interconnects is also studied. Using on-board wires the global clock frequency of a projected system-on-a-chip in year 2011 can be increased by about 45% and the required silicon area for repeaters can also be reduced by 60%, using adequate repeater insertion.

Keywords

VLSI; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; microprocessor chips; general model; high global clock frequency; high wiring density; number of repeaters; on-board interconnects; on-board wires; on-chip interconnects; optimal partition; reduced silicon area; repeater size; system-on-a-chip; Clocks; Delay; Frequency; Packaging; Repeaters; System-on-a-chip; Transistors; Wafer scale integration; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International

Conference_Location

Burlingame, CA, USA

Print_ISBN

0-7803-6678-6

Type

conf

DOI

10.1109/IITC.2001.930038

Filename

930038