DocumentCode
3193867
Title
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems
Author
Sugihara, Makoto
Author_Institution
Toyohashi Univ. of Technol., Toyohashi
fYear
2008
fDate
17-19 March 2008
Firstpage
757
Lastpage
762
Abstract
Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue for embedded systems, which is vulnerability to single event upsets (SEUs), has become a matter of concern as technology proceeds. This paper presents robustness of heterogeneous multiprocessor systems to SEUs and proposes task scheduling for minimizing SEU vulnerability of them. This paper experimentally shows that increasing performance of a CPU core deteriorates its reliability. Based on the experimental observation, we propose task scheduling for reducing SEU vulnerability of a heterogeneous multiprocessor system. The experimental results demonstrate that our task scheduling technique can reduce much of SEU vulnerability under real-time constraints.
Keywords
integrated circuit reliability; integrated circuit testing; microprocessor chips; multiprocessing systems; heterogeneous multiprocessor systems; integrated circuit reliability; single event upsets; task scheduling; Circuit simulation; Computational modeling; Computer errors; Embedded computing; Embedded system; Multiprocessing systems; Power system reliability; Processor scheduling; Random access memory; Single event upset; Heterogeneous Multiprocessor Systems; Reliability; Single Event Upset; Soft Error; Task Scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
978-0-7695-3117-5
Type
conf
DOI
10.1109/ISQED.2008.4479833
Filename
4479833
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