Characterization of chip-to-chip wireless interconnections based on capacitive coupling

Author

Cardu, R. ; Franchi, E. ; Guerrieri, R. ; Scandiuzzo, Mauro ; Cani, S. ; Perugini, L. ; Spolzino, S. ; Canegallo, R.

Author_Institution

ARCES, Univ. of Bologna, Bologna, Italy

fYear

2010

fDate

27-29 Sept. 2010

Firstpage

375

Lastpage

380

Abstract

3D chip-to-chip capacitive interconnections are in common practice characterized with FEM solvers as they cannot be modeled as lumped RLC circuits as ohmic 3D interconnects. This paper describes some drawbacks of this procedure and proposes an innovative flow, based on post-layout parasitic extraction tools, to enable the designer to place capacitive interconnects as constrained macros in a digital design flow.

Keywords

circuit layout CAD; digital integrated circuits; finite element analysis; integrated circuit interconnections; integrated circuit layout; three-dimensional integrated circuits; 3D chip-to-chip wireless interconnections; FEM solvers; capacitive coupling; capacitive interconnects; digital design flow; innovative flow; lumped RLC circuits; ohmic 3D interconnects; post-layout parasitic extraction tools; Capacitance; Couplings; Electrodes; Finite element methods; Integrated circuit interconnections; Solid modeling; Three dimensional displays; 3D extraction flow; 3D integration; capacitive coupling; face-to-face; wireless interconnections;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP

Conference_Location

Madrid

Print_ISBN

978-1-4244-6469-2

Type

conf

DOI

10.1109/VLSISOC.2010.5642690

Filename

5642690