A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole

Author

Do, Aaron V. ; Boon, M.C. ; Do, Manh Anh ; Yeo, Kiat Seng ; Cabuk, Alper

Author_Institution

Nanyang Technol. Univ., Singapore, Singapore

fYear

2010

fDate

27-29 Sept. 2010

Firstpage

381

Lastpage

386

Abstract

A novel passive mixer architecture is proposed which uses a voltage-mode passive mixer with a tuned output pole. Using this technique, it is shown that the IF section´s IIP₃ requirements are relaxed by up to 33 dB for the IEEE 802.15.4 standard. This allows for use of an ultralow power IF section without linearity compensation. The overall receiver front end consisting of an LNA, a mixer and a third-order channel-select filter is designed in 0.18 μm CMOS technology with a 1-V supply voltage, and post-layout simulations show a 5 dB NF with only 1.7-mW total power consumption.

Keywords

CMOS integrated circuits; filters; low-power electronics; mixers (circuits); personal area networks; CMOS ultralow-power receiver front end; IEEE 802.15.4 standard; noise figure 5 dB; power 1.7 mW; size 0.18 mum; third-order channel-select filter; tuned passive mixer output pole; voltage 1 V; voltage-mode passive mixer; CMOS integrated circuits; CMOS technology; Mixers; Noise measurement; Radiation detectors; Radio frequency; Tuners; CMOS RF Integrated Circuits; Low Power; RF Front End; System on Chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP

Conference_Location

Madrid

Print_ISBN

978-1-4244-6469-2

Type

conf

DOI

10.1109/VLSISOC.2010.5642691

Filename

5642691