A platform-based SoC design for a multi-standard audio decoder

In complex SoC design, the reusable IP is very useful to achieve the whole system with high verification. Based on this issue, a hardware and software (HW/SW) co-design approach can obtain maximum performance, and is easily integrated with the other functions to complete the system. This paper presents the multi-standard audio decoder design with hardware/software co-design flow. First we need to generate the deliverable IP as the hardware design part, and then construct the other modules as software design part. In order to save the hardware cost, the hardware accelerator is applied with the fast algorithm and some techniques on architecture design. Not only just an implementation on the complex system design, our design flow can help designer to profile and analyze the performance in system level. With an aid on it, we can provide a multi-standard decoder with hardware accelerator to improve system performance. The implement result shows that it only needs 3.6 MHz in real-time constraint. With this low operation frequency, the multi-standard audio decoder with HW/SW co-design approach can take advantage on low power constrained application, especially on portable device.